Latch-up is an adverse effect occurring in Complementary Metal-Oxide Semiconductor (CMOS) devices when a significant current flows through a Si substrate between N-type Metal-Oxide Semiconductor device (NMOS) and P-type Metal-Oxide Semiconductor device (PMOS) parts of CMOS structure and degrades its performance. Latch-up occurs when certain bias conditions trigger a parasitic structure of two parasitic bipolar transistors, thus creating an inadvertent low-impedance path between the power supply rails of a Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) circuit and provide high conductivity path between NMOS and PMOS parts of the device. This disrupts proper functioning of the part and possibly even leading to its destruction due to excessive amount of current. A power cycle is required to correct this situation.
The parasitic structure is usually equivalent to a thyristor or Semiconductor-Controlled Rectifier (SCR), a PNPN structure that acts as a PNP and an NPN transistor stacked next to each other. During a latch-up when one of the transistors is conducting, the other one begins conducting, too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it, which usually means that it remains until a power-down.
The latch-up does not have to happen between the power rails; it can happen at any place where the required parasitic structure exists. A spike of positive or negative voltage on an input or output pin of a digital chip, exceeding the rail voltage by more than a diode drop, is a common cause of latch-up. Another cause is the supply voltage exceeding the absolute maximum rating, often from a transient spike in the power supply, leading to a breakdown of some internal junction. This frequently happens in circuits which use multiple supply voltages that do not come up in the proper order after a power-up, leading to voltages on data lines exceeding the input rating of parts that have not yet reached a nominal supply voltage.
Latch-up happening in a parasitic structure from P+ in n-well (high voltage supply n-well, HVNW) connected to a high voltage supply to N+ in n-well (low voltage supply n-well, LVNW) connected to a low voltage supply is worse than in a parasitic structure from P+ in HVNW to N+ in p-well (PW) connected to either high or low voltage, especially in high voltage tolerant (HVT) Input/Output (I/O) library application, e.g. for 2.5 V/3.3 V tolerant to 3.3 V/5.5 V HVT I/O library. It is due to the substrate resistance of N+ in LVNW is larger than N+ in PW, as a result, the βnpn is larger for N+ in LVNW case. As for HVT I/O library, since it needs to sustain input of high voltage from 3.3 V to 5 V (power supply) in some applications, the voltage difference between HVNW and LVNW is larger than non-HVT I/O library.
One way to avoid the latch-up problem is to enlarge the latch-up path spacing, i.e. the space between P+ in HVNW to N+ in LVNW. For example, using a current trigger testing (a test that injects (+/−) current to I/O pad and evaluates the latch-up behavior), a proper spacing can be determined. In a latch-up current injection testing, an exemplary circuit with the signal I/O pad with HVNW abutting on the low voltage power pad with LVNW cannot pass the test and latch-up occurs between the HVNW and LVNW. However, the circuit could pass the latch-up testing when at least 30 μm spacing was provided in between the HVNW and LVNW by inserting another signal I/O pad between the HVNW (existing signal I/O pad) and LVNW (low voltage power pad).
However, the extra space increases the design area and results in larger area impact by inefficient use of the chip area. This is a problem especially for ultra-small HVT cell designs. Considering that the scale of integrated circuits is constantly shrinking for higher density and more efficient use of the chip area, increased spacing is contrary to the design objective. Further, even after increasing the latch-up path spacing, latch-up can still happen depending on potential extreme conditions, due to the voltage difference between HVNW (e.g. 3.3 V or 5 V) to LVNW (e.g. 1.2 V).
Accordingly, new structure and method for latch-up prevention in integrated circuits, particularly for ultra-small HVT cell are desired.